Dynamic random access memories (DRAMs) are a widely used form of semiconductor memory. DRAMs are composed of a memory cell array and peripheral circuitry. Each memory cell array is formed of a plurality of memory cells for storing information. Typical memory cells are formed with a transistor for accessing a capacitor that stores charge. Of primary concern is maximizing the storage capacitance of each memory cell capacitor. This need is particularly acute in light of the demand for high density DRAMs, without increasing the chip area required to form the cell and, preferably, allowing a decrease in the chip area per cell.
One way to achieve greater capacitance per cell is to increase the surface area of the capacitor electrodes without increasing the respective cell area. As can be seen from the following equation, capacitance, C, is roughly determined by the thickness of the capacitor insulator (t.sub.ox), the surface area of the capacitor electrodes (A), and the dielectric constant of the capacitor insulator (68). EQU C=(.epsilon..multidot.A)/t.sub.ox
Increasing the surface area of the capacitor electrodes by forming the storage capacitor in a container like shape is well known in the art. To further increase circuit density in DRAMs stacked capacitors are used. These capacitors are actually stacked on top of the substrate, which may or may not include access devices. Two or more layers of a conductive material called electrodes are formed of polysilicon or poly are deposited over the substrate with dielectric layers sandwiched between each electrode.
U.S. Pat. No. 5,340,765 to Dennison et al., herein incorporated by reference, describes a method for further increasing the capacitance of a bottom electrode of such capacitors by forming the electrode surfaces with hemispherical grained polysilicon (HSG) which increases the surface area of the electrodes. First, a portion of an oxide layer covering access circuitry on a semiconductor wafer is removed to form a container. A bottom electrode is then formed by growing a first amorphous silicon layer. A first insulating layer is then formed on the first amorphous silicon layer. Then, a doped silicon layer is formed on the first insulating layer. Subsequently a second insulating layer is formed on the doped silicon layer. Finally, a second amorphous silicon layer is formed on the second insulating layer.
The insulating layers may be formed of oxide or nitride, and freeze the grain boundaries during deposition of the layers. Both the first and second amorphous silicon layers, and the insulating layers are formed relatively thin in relation to the doped silicon layer.
After formation of the layers, the wafer is planarized and the oxide etched to form standing containers which are then annealed to form HSG on both sides of the doped silicon layer. The insulating layers keep the doped silicon layer intact such that the silicon atoms do not penetrate silicon interfacing layers. Formation of a dielectric layer and top capacitor plate complete the capacitor formation.
There is a need for an improved stacked capacitor which may be etched better. There is a further need for a stacked capacitor container with improved HSG formation and better migration of dopants during HSG formation. There is yet a further need to improve the formation of multiple layers of silicon in a stacked capacitor container. There is also a need to enhance the capacitance of stacked capacitors, and provide a capacitor with higher breakdown voltage which is less susceptible to charge depletion.